1. Field of the Invention
The present invention relates to a semiconductor device including a circuit constituted by thin film transistors (hereinafter referred to as TFTs) and a method of fabricating the same. For example, the invention relates to an electro-optical device typified by a liquid crystal display panel, and an electronic apparatus incorporating such an electro-optical device as a component.
Note that in the present specification, the term xe2x80x9csemiconductor devicexe2x80x9d indicates any devices capable of functioning by using semiconductor characteristics, and all of the electro-optical devices, semiconductor circuits, and electronic apparatuses are semiconductor devices.
2. Description of the Related Art
In recent years, attention has been paid to a technique to construct a thin film transistor (TFT) by using a semiconductor thin film (thickness of several to several hundreds nm) formed over a substrate having an insulating surface. The thin film transistor is widely used for an electronic device such as an IC or electro-optical device, and its development is hastened especially as a switching element of an image display device.
As a semiconductor thin film forming an active layer of a TFT, although a noncrystalline silicon film (typically an amorphous silicon film) has been often used. a demand for a TFT having a faster operation speed is increased, and a crystalline silicon film (typically a polysilicon film) has become the mainstream. As a technique for obtaining the crystalline silicon film, a method in which after an amorphous silicon film is formed, the film is crystallized by a heat treatment or irradiation of laser light, is often used.
Besides, there is disclosed a technique (Japanese Patent Unexamined Publication No. Hei. 6-232059 and No. Hei. 7-321339) in which after an amorphous silicon film is formed, a catalytic element (for example, nickel) for promoting crystallization of the amorphous silicon film is introduced, and a heat treatment is carried out to obtain a crystalline silicon film. According to this technique, it is possible to obtain a uniform crystalline silicon film in a short time.
However, the catalytic element for promoting crystallization of the amorphous silicon film often deteriorates the characteristics of the TFT. Then after crystallization, a region where the catalytic element exists at a high concentration is removed by etching or the like.
Hereinafter, a specific description will be made on a crystallizing technique using a catalytic element for promoting crystallization of an amorphous silicon film, and a technique for removing a region where the catalytic element exists at a high concentration.
In FIGS. 1A and 1B, reference numeral 101 designates a silicon film; 102, a beltlike region on a silicon film surface (hereinafter referred to as a catalytic element introduction region); and 103, a silicon oxide mask covering the silicon film surface other than the catalytic element introduction region. Note that by using the silicon oxide mask 103, the catalytic element is selectively introduced into the catalytic element introduction region 102.
First, the catalytic element is introduced into the catalytic element introduction region 102, and by carrying out a heat treatment, crystals are made to grow from the catalytic element introduction region 102 in a direction parallel to an insulating surface and a direction almost vertical to a long side of the catalytic element introduction region 102. Note that reference numeral 104 designates the direction of crystal growth.
A leading end portion of crystal growth obtained in this way is designated by 105. It is known that the catalytic element of high concentration exists in the leading end portion 105 of the crystal growth. When a crystal growth distance exceeds some value, a region where an active layer of a TFT can be disposed is formed between the beltlike catalytic element introduction region 102 and the leading end portion 105 of the crystal growth where the catalytic element exists at a high concentration.
Next, when the active layer of the TFT is formed using the region sandwiched between the leading end portion 105 of the crystal growth and the beltlike catalytic element introduction region 102, other regions (including at least the leading end portion 105 of crystal growth) where the catalytic element exists at a high concentration are removed by etching.
Conventionally, the arrangement of the catalytic element introduction region is determined so that a region which becomes an active layer of a TFT in a subsequent step exists in the region sandwiched between the leading end portion 105 of the crystal growth and the beltlike catalytic element introduction region 102, and a heat treatment condition for crystallization is determined.
Conventionally, it has been considered to be appropriate that the arrangement of the catalytic element introduction region is determined so that the region which becomes the active layer of the TFT in the subsequent step exists in the region sandwiched between the leading end portion of the crystal growth and the catalytic element introduction region. Besides, even if the catalytic element is removed in a step subsequent to crystallization, since it is difficult to completely remove the catalytic element, it has been considered to be sufficient if a necessary minimum amount of catalytic element is introduced.
Thus, one catalytic element introduction region has been provided at one side of the region which becomes the active layer of the TFT in the subsequent step. Note that a crystal growth velocity at 570xc2x0 C. in the case where only one catalytic element introduction region (width w=10 xcexcm) was disposed was about 3 xcexcm/hr.
The present inventors paid attention to the fact that crystal growth conditions greatly depend on the width of a catalytic element introduction region and an arrangement interval, and found a method for effectively performing crystal growth as compared with a conventional technique.
An object of the present invention is to provide a semiconductor device and a method of fabricating the same in which a heat treatment time required for crystal growth is shortened as compared with a conventional technique and a process is simplified.
Another object of the present invention is to provide a semiconductor device and a method of fabricating the same in which catalytic element introduction regions are effectively arranged in a small space, to meet requirements in recent years that a circuit is made minute and is integrated.
A structure of the present invention disclosed in the present specification relates to a semiconductor device comprising a TFT provided on a substrate having an insulating surface, characterized in that an active layer of the TFT is made of a crystalline semiconductor film formed through crystal growth from a plurality of regions where a catalytic element for promoting crystallization is introduced, the active layer of the TFT includes a channel forming region, a source region, and a drain region, and the source region or drain region includes a boundary portion of regions formed through crystal growth from the plurality of regions.
That is, in the present invention, it is characterized in that at least one of active layer of the TFT includes a first region that has been crystal grown from one region where a catalytic element is introduced and a second region that has been crystal grown from another region where a catalytic element is introduced.
Further, another structure of the present invention relates to a semiconductor device comprising a TFT provided on a substrate having an insulating surface, characterized in that an active layer of the TFT is made of a crystalline semiconductor film formed through crystal growth from a plurality of regions where a catalytic element for promoting crystallization is introduced, the active layer of the TFT includes a plurality of channel forming regions, and a region sandwiched between the plurality of channel forming regions includes a boundary portion of regions formed through crystal growth from the plurality of regions.
Still further, another structure of the present invention relates to a semiconductor device comprising a CMOS circuit constituted by an n-channel TFT and a p-channel TFT on a substrate having an insulating surface, characterized in that an active layer of each of the n-channel TFT and the p-channel TFT is made of a crystalline semiconductor film formed through crystal growth from a plurality of regions where a catalytic element for promoting crystallization is introduced, the active layer of each of the n-channel TFT and the p-channel TFT includes a channel forming region, a source region, and a drain region, and the source region or drain region of the n-channel TFT includes a boundary portion of regions formed through crystal growth from the plurality of regions.
Yet further, another structure of the present invention relates to a semiconductor device comprising a CMOS circuit constituted by an n-channel TFT and a p-channel TFT on a substrate having an insulating surface, characterized in that an active layer of each of the n-channel TFT and the p-channel TFT is made of a crystalline semiconductor film formed through crystal growth from a plurality of regions where a catalytic element for promoting crystallization is introduced, the active layer of each of the n-channel TFT and the p-channel TFT includes a channel forming region, a source region, and a drain region, and the source region or drain region of the p-channel TFT includes a boundary portion of regions formed through crystal growth from the plurality of regions.
In the above-mentioned respective structures, it is characterized in that the boundary portion is formed in a region where a region formed through crystal growth from a first region where the catalytic element is introduced collide with a region formed through crystal growth from a second region where the catalytic element is introduced.
Further, in the above-mentioned respective structures, it is characterized in that the boundary portion has a linear shape.
In addition, a structure of the present invention realizing the above-mentioned structure relates to a method of fabricating a semiconductor device, comprising the steps of: forming an amorphous semiconductor film; introducing a catalytic element for promoting crystallization in the amorphous semiconductor film selectively; forming a boundary portion by a heat treatment to cause crystal growth from a plurality of regions where the catalytic element is introduced; removing or reducing the catalytic element existing in a region formed through crystal growth; and forming an active layer of a TFT by using the region where the catalytic element is removed or reduced.
Further in the above-mentioned structure, it is characterized in that the step of selectively introducing the catalytic element is carried out by using a mask having an opening portion for exposing a part of the amorphous semiconductor film, and the mask includes a plurality of opening portions at both sides of the boundary portion.
Still further, in the above-mentioned respective structure, it is characterized in that a source region or drain region of the TFT including the boundary portion is formed.
Yet further, in the above-mentioned respective structure, it is characterized in that a channel forming region of the TFT is formed between the opening portion and the boundary portion.
Furthermore, in the above-mentioned respective structure, it is characterized in that the catalytic element for promoting crystallization is one kind or plural kinds of elements selected from the group consisting of Ni, Fe, Co, Cu, Ge, and Pd.